Power MOSFETs and Gate Driving Techniques: Rds(on), Miller Plateau, High-Side Switching & Thermal Sizing

Power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) dominate power electronics from a few Watts up to multiple kilowatts. Understanding their gate capacitance charging behavior, switching losses, and thermal limits is essential for motor drives, inverters, and battery disconnect systems.

1. Structural Physics: Planar vs Trench vs Superjunction

Modern power MOSFETs use vertical DMOS or trench structures where current flows vertically from the top source metallization through the substrate to the bottom drain tab. Trench gates maximize channel density, dramatically reducing on-state resistance R_DS(on) down to milliohms.

2. The Gate Charge (Qg) Dynamic & Miller Plateau

Because the gate is insulated by silicon dioxide (SiO2), it acts as a non-linear capacitive network (C_gs, C_gd, C_ds). When turning ON a MOSFET with gate driver voltage V_drv:

• Phase 1: Gate-to-source capacitance C_gs charges up to threshold voltage V_th. Drain current I_d remains zero.

• Phase 2: Drain current ramps up to full load current while drain-source voltage V_ds remains high.

• Phase 3 (Miller Plateau): Drain-to-gate capacitance C_gd (Miller capacitance) absorbs all gate current as V_ds collapses toward zero. Gate voltage V_gs remains flat at V_plateau.

• Phase 4: Gate charges from V_plateau to final drive voltage, driving R_DS(on) to its lowest catalog rating.

3. Gate Driver Peak Current Calculation

To achieve transition time t_sw (e.g. 50 nanoseconds) across Miller charge Q_gd: