Embedded Communication Protocols Breakdown: UART, I2C, SPI and CAN Bus In-Depth Comparison

Modern microcontrollers interface with sensors, displays, memories, and industrial networks using standard digital serial communication protocols. Each protocol strikes a distinct balance between pin count, transmission distance, bandwidth, and noise immunity.

1. UART (Universal Asynchronous Receiver-Transmitter)

UART is an asynchronous, point-to-point, full-duplex protocol requiring only two signal lines: TX and RX. Because there is no shared clock line, both transmitter and receiver must agree in advance on baud rate (e.g., 9600, 115200, 921600 bps), data bits, parity, and stop bits.

Data is framed with a logic LOW start bit followed by 8 data bits (LSB first), optional parity, and 1 or 2 logic HIGH stop bits. Timing drift must remain within ±2.5% to avoid sampling errors.

2. I2C (Inter-Integrated Circuit) Bus

I2C is a synchronous, multi-master, multi-slave, half-duplex bus using two open-drain bidirectional wires: SDA (Serial Data) and SCL (Serial Clock). Devices have unique 7-bit or 10-bit addresses.

Pull-Up Resistor Calculation: Because lines are open-drain, pull-up resistors (R_p) are required. Maximum value depends on bus capacitance (C_bus <= 400 pF):

R_p(max) = t_rise / (0.8473 * C_bus)

For Fast-Mode (400 kHz, max t_rise = 300 ns) with C_bus = 150 pF: R_p(max) = 300ns / (0.8473 * 150pF) ≈ 2.36 kOhms. Typically, 2.2k or 4.7k resistors are chosen.

3. SPI (Serial Peripheral Interface)

SPI is a synchronous, single-master, multi-slave, full-duplex 4-wire bus: MOSI, MISO, SCK, and CS/SS (Chip Select per slave). Operates at speeds exceeding 50 MHz with zero protocol overhead or address decoding delay.

Modes are determined by CPOL (Clock Polarity) and CPHA (Clock Phase) combinations (Modes 0, 1, 2, 3).